Electronics Engineering

GENERAL BASIC CONCEPTS Effects of technology evolution, Physical implementation alternatives, fundamentals of intergated circuit layout, Analysis of integrated systems’ production costs THE DESIGN FLOW Abstraction levels, “Y” diagram, Analysis and verification tools THE VHDL HARDWARE DESCRIPTION LANGUAGE Introduction, VHDL objects, delay model, concurrent statements, VHDL processes, sequential control statements, procedures and functions, packages and libraries, structural descriptions, quick review of other possibly useful statements. REGISTER TRANSFER LEVEL DESIGN OF “HARDWIRED” EMBEDDED SYSTEMS Register transfer level (RTL) synthesis, Design example: a simple edge detection filter for image processing, Data-path synthesis analysis, In-depth concepts of RTL timing REGISTER TRANSFER LEVEL DESIGN OF “SOFTWARE/HARDWARE” EMBEDDED SYSTEMS Specification of a very simple microprocessor for edge detection, RTL design of the microprocessor, in-depth concepts on the control-path implementation, Quantitative laws on digital system performance. COMMUNICATION SUBSYSTEMS Fundamental problems, On-chip communications: from buses to NoCs, Off-chip communications: evolving standards FUNDAMENTAL CONCEPTS ON MICROPROCESSOR ARCHITECTURES General ideas, Rules of the RISC approach, fundamentals of post-RISC architectures, quick overview of superscalar architectures, VLIW architectures Richiami e concetti generali, Regole dell’approccio RISC, Concetti generali sulle architetture post-RISC, Cenni sulle architetture superscalari, Architetture VLIW COMBINATIONAL CIRCUITS FOR HIGH PERFORMANCE SYSTEMS In-depth analysis of CMOS logic principles, conventional static CMOS, pseudo-NMOS and DCVSL, pass-transistor logic, Dynamic logic MEMORY CIRCUITS Latches and flip-flops, memory circuit structures: decoders, cell arrays; CLOCKING STRATEGIES Circuit structures for synchronization, Example: the classic PLA, Example: superscalarissue logic ARITHMETIC PROCESSING SUBSYSTEMS Introduction, fast adder structures, fast multiplier structures, other basic arithmetic units. SPEED OPTIMIZATION IN LOGIC CIRCUITS Introduction, the logical effort model of CMOS logic delay, multi-level logic delay modeling and optimization, modeling complex logic delay BASIC CONCEPTS ON LOW POWER DESIGN Preliminary concepts, power models of CMOS logic, estimation techniques, design techniques BASIC CONCEPTS ON ASYNCHRONOUS DESIGN General concepts, components and metodologies for self-timed systems, self-timed data-path functional units LAB EXPERIENCES ON CMOS CIRCUIT SIMULATION LAB EXPERIENCES ON VHDL/SYSTEMVERILOG SIMULATION AND SYNTHESIS ON FPGA

fundamentals of digital circuits, combinational and sequential logic synthesis, microprocessor systems

Weste and Eshraghian, Principles of CMOS VLSI design. Jan M. Rabaey: Digital Integrated Circuits: a Design Perspective, Prentice Hall. Waine Wolf, Modern VLSI Design, Prentice Hall. Slides and articles available at http://vlsi.diet.uniroma1.it and on the Google Classroom of the course

lectures, flipped class exercises, occasionalmente lezioni in remoto, lab experiences

written + compulsory project

to be specified in the classroom

lectures, flipped class exercises, occasionalmente lezioni in remoto, lab experiences

- Digital circuit simulation with NGSPICE - VHDL simulation with Modelsim - RTL synthesis on FPGA: synthesizable VHDL, synthesis with Xilinx - RTL synthesis on ASIC: synthesis with Synopsys Design Compiler

Digital electronic circuits, VHDL language programming.

The laboratory is based on course handouts dristributed on elearning.uniroma1.it

Mandatory attendance for the laboratory experieces

Written open questions on the applications developed during the laboratory.