Electronics Engineering

GENERAL BASIC CONCEPTS Effects of technology evolution, Physical implementation alternatives, fundamentals of intergated circuit layout, Analysis of integrated systems’ production costs THE DESIGN FLOW Abstraction levels, “Y” diagram, Analysis and verification tools THE VHDL HARDWARE DESCRIPTION LANGUAGE Introduction, VHDL objects, delay model, concurrent statements, VHDL processes, sequential control statements, procedures and functions, packages and libraries, structural descriptions, quick review of other possibly useful statements. COMBINATIONAL CIRCUITS FOR HIGH PERFORMANCE SYSTEMS In-depth analysis of CMOS logic principles, conventional static CMOS, pseudo-NMOS and DCVSL, pass-transistor logic, Dynamic logic MEMORY CIRCUITS Latches and flip-flops, memory circuit structures: decoders, cell arrays; CLOCKING STRATEGIES Circuit structures for synchronization ARITHMETIC PROCESSING SUBSYSTEMS Introduction, fast adder structures, fast multiplier structures, other basic arithmetic units. SPEED OPTIMIZATION IN LOGIC CIRCUITS Introduction, the logical effort model of CMOS logic delay, multi-level logic delay modeling and optimization, modeling complex logic delay BASIC CONCEPTS ON LOW POWER DESIGN Preliminary concepts, power models of CMOS logic, estimation techniques, design techniques LAB EXPERIENCES ON CMOS CIRCUIT SIMULATION LAB EXPERIENCES ON VHDL/SYSTEMVERILOG SIMULATION AND SYNTHESIS ON FPGA

fundamentals of digital circuits, combinational and sequential logic synthesis, microprocessor systems

Weste and Eshraghian, Principles of CMOS VLSI design. Jan M. Rabaey: Digital Integrated Circuits: a Design Perspective, Prentice Hall. Waine Wolf, Modern VLSI Design, Prentice Hall. Slides and articles available at http://vlsi.diet.uniroma1.it and on the Google Classroom of the course

lectures, flipped class exercises, occasionalmente lezioni in remoto, lab experiences

written exam + laboratory exam

to be specified in the classroom

lectures, flipped class exercises, occasionalmente lezioni in remoto, lab experiences

- Digital circuit simulation with NGSPICE - VHDL simulation with Modelsim - RTL synthesis on FPGA: synthesizable VHDL, synthesis with Xilinx - RTL synthesis on ASIC: synthesis with Synopsys Design Compiler

Digital electronic circuits, VHDL language programming.

The laboratory is based on course handouts dristributed on elearning.uniroma1.it

Mandatory attendance for the laboratory experieces

Written open questions on the applications developed during the laboratory.